1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of Related Art
CSPs (Chip Size Packages) are known as semiconductor chip package structures. The adoption of a CSP makes it possible to make the size of the package substantially the same as the chip cut from the semiconductor wafer.
WCSPs, which constitute one type of CSP, are known. Japanese Patent No. 3313547, for example, is known as a publication that discloses a WCSP.
A WCSP structure comprises a redistribution wiring layer which is provided on the surface on which the integrated circuit is formed. External terminals, that is, input/output pins, are provided on the redistribution wiring layer. The redistribution wiring layer comprises wiring for connecting external terminals to the pads of the integrated circuit. In the above-mentioned publication, solder balls are employed as the external terminals. The surface on which the external terminals are formed is called the ‘mount face’ and a structure in which external terminals are provided on a mount face is known as a ‘fan-in structure’.
The maximum number of external terminals which can be provided on the mount face is determined by the pitch of the external terminals and the size of the mount face. In other words, in order to increase the quantity of external terminals provided on the mount face, the pitch of the external terminals must be reduced or the mount face must be increased in size.
In many cases, the pitch of the external terminals is designated by the user of the semiconductor device. In cases where the pitch is designated beforehand, it is not possible to increase the number of terminals by reducing the pitch. In addition, the reduction in pitch is subject to fabrication technology limitations.
On the other hand, in a case where the size of the mount face is increased, although the chip area is then larger, the maximum number of external terminals which can be provided on the mount face can be optionally set. In order to increase the size of the mount face, the degree of integration of the integrated circuit may be reduced.
In a case where the degree of integration of the integrated circuit formed in the semiconductor chip is reduced, it is undesirable to use this semiconductor chip for fabricating a semiconductor device with a package structure other than a WCSP structure (a wire bonding structure, for example). This is because, when wire bonding structure packaging or other non-WCSP packaging is performed on a semiconductor chip with a small degree of integration, the size of the semiconductor device is then abnormally large. Therefore, even when the logic structure of the integrated circuit is the same, a chip mounted on the WCSP and a chip mounted on another type of package should be designed separately and fabricated by means of a separate process. For this reason the design and fabrication process cannot be shared, and so the fabrication costs are extremely high.